The present invention pertains to the field of electronic design automation. More particularly, aspects of the present invention pertain to methods and systems for automatic test pattern generation (ATPG).
The rapid growth of the complexity of modern electronic circuits has forced electronic circuit designers to rely upon computer programs to assist and automate most steps of the circuit design process. Typical circuits today contain hundreds of thousands or millions of individual pieces or xe2x80x9ccells.xe2x80x9d Such a design is much too large for a circuit designer or even a team of engineers to effectively manage manually. To automate the circuit design and fabrication of integrated circuit devices, electronic design automation (EDA) systems have been developed.
An EDA system is a computer software system designers use for designing integrated circuit (IC) devices. The EDA system typically receives one or more high level behavioral descriptions of an IC device (e.g., in HDL languages like VHDL, Verilog, etc.) and translates this behavioral description into netlists of various levels of abstraction. At a higher level of abstraction, a generic netlist is typically produced based on technology independent primitives. A netlist describes the IC design and is composed of nodes (elements) and edges, e.g., connections between nodes, and can be represented using a directed cyclic graph structure having nodes which are connected to each other with signal lines. The netlist description is typically stored in computer readable media within the EDA system and processed and verified using many well known techniques. The EDA system ultimately produces a physical device layout in mask form which can be used to directly implement structures in silicon to realize the physical IC device.
Due to complications in the fabrication process, some fabricated IC devices may not be fully functional. Therefore, chip testing must be performed before shipment to customers. In order to facilitate chip-testing, some ICs include special logic circuits that are designed for enhancing testability (e.g., scan chains). In addition, some EDA systems include automatic test pattern generation (ATPG) processes for analyzing the various representations of the netlist designs and for automatically generating test patterns therefrom. A test pattern is created for a fault modeled in the design such that when the fault exists the observable behavior of the correctly operable IC would be different than that of an IC without that fault present. In order to perform this function, the test pattern needs to control the behavior of the design at the fault site such that it differs in the good and faulty circuits and then the difference has to be observed at a point that is measurable in the design.
As devices enter the sub-micron era, the task of devising test patterns that can achieve reasonable fault coverage becomes increasingly difficult. To exhaustively test the combinational circuitry of such sub-micron designs, a very large number of test patterns are required to test all faults in the design. A single test pattern can detect a number of faults simultaneously and there is a correlation between the number of faults detected by a pattern and the number of inputs that need to be constrained to detect the faults. If the requirements to control and observe a fault require too many inputs of the design to be controlled then the tests for different faults most probably conflict in some position and unique tests would be needed to detect different faults. These factors lead to the explosion in test data volume.
The number of test patterns has a significant impact on the costs associated with testing the integrated circuits. For instance, as the number of tests increases, the time required for testing the ICs will be longer. In addition, automatic testing equipment (ATE) must be constantly upgraded with more and more memory in order to cope with the increasing test data volume. Further, more time is needed for generating a very large number of test patterns.
Therefore, what is needed is a method and system for controlling test data volume in deterministic ATPG. What is also needed is a method and system for reducing test data volume without sacrificing fault coverage.
Accordingly, the present invention provides a method and system for controlling test data volume in deterministic ATPG by test point insertion. The present invention also provides a method and system for inserting test points in a cost effective and minimally intrusive manner. Effective insertion of test points increases the number of observable and/or controllable points thereby augmenting the process of deterministic test pattern generation and reducing the number of test vectors required for testing integrated circuits.
In accordance with an embodiment of the present invention, a fault list having all the potential faults of an input integrated circuit design is initialized and all the potential faults are marked as untestable. Then, a set of deterministic test patterns, T, for testing several of the potential faults are generated by ATPG. A fault simulation process is then performed on the integrated circuit design with the test patterns, T, to mark off additional detectable faults. Significantly, during fault simulation, fault propagation is monitored to determine the nets in the design to which untested faults propagate. The nets at which fault propagation discontinues (e.g., where they are blocked off if the fault effect does not reach an observable point) are also monitored. This information is collected over the sets of test patterns, T, that are fault simulated. Based on this fault propagation information, particular ones of the nets are selected for test point insertion such that, when the test points are inserted, additional faults would be detected by the set of test patterns, T. These steps are then repeated for another set of test patterns until the desired fault coverage is achieved, significantly reducing test data volume.
In one embodiment, the nets to which most untested faults propagate are selected for test point insertion to create observability. The number of test points selected may be determined by user-defined parameters. Further, according to an embodiment of the present invention, observe point circuits and control point circuits may be inserted.
Specifically, embodiments of the present invention include an electronic design automation system that comprises: a processor; a bus coupled to the processor; and a computer readable memory coupled to the bus and having stored therein computer readable program code for causing the electronic design automation system to perform a method of improving fault coverage of test patterns for testing integrated circuits. In one embodiment, the method comprises the steps of: a) accessing a netlist description of an integrated circuit design that include logic cells intercoupled by nets; b) generating a set of test patterns for testing a set of potential faults; c) monitoring fault propagation of the untested potential faults during fault simulation; d) generating fault propagation information of the untested potential faults; and e) based on the fault propagation information, selecting appropriate nets for test point insertion for causing some of the untested potential faults to become detectable by the set of test patterns.